*** DNM*** PoC for no wait in multi-pipeline-set-state - #11072
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serhiy-katsyuba-intel wants to merge 5 commits into
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*** DNM*** PoC for no wait in multi-pipeline-set-state#11072serhiy-katsyuba-intel wants to merge 5 commits into
serhiy-katsyuba-intel wants to merge 5 commits into
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Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
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Looks nice a solution to me. Trigger order is kept, 1ms delay is removed and pipeline states still happen at start of LL ticks (= the original reason why trigger processing was delayed to LL thread).
| const struct sof_uuid_entry *uid; /**< Uuid */ | ||
| uint16_t type; /**< type of the task (LL or EDF) */ | ||
| uint16_t priority; /**< priority of the task (used by LL) */ | ||
| int16_t priority; /**< priority of the task (used by LL); lower runs first */ |
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Need to check do we have a hard limit for max priority (e.g. can we fit max valid priority to a signed 16bit variabe)
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Vibe-coded PoC to sort of revert #8504